Due to a continual increase in the integration density of semiconductor devices such as dynamic random access memories (DRAMs), various methods have been considered for obtaining sufficient cell capacitance in a limited area. For example, methods for providing sufficient cell capacitance include, e.g., using a dielectric material having a high dielectric constant as a dielectric layer of a capacitor, reducing the thickness of the dielectric layer, or increasing an effective area of a lower electrode.
Among these conventional methods, the use of a material having a high dielectric constant requires time and money for introducing new equipment, verifying reliability, mass producing the dielectric layer, and lowering the temperature of subsequent processes. Therefore, the method of increasing the effective area of the lower electrode is more favorable since a conventional dielectric layer can still be used where the manufacturing process is relatively easy to employ.
There are also several methods that can be implemented for increasing the effective area of a lower electrode for a capacitor. For instance, the lower electrode can be made to be three dimensional, for example, a cylinder-type or fin-type, and the height of the lower electrode can be increased. The process of shaping the lower electrode to be three dimensional and cylindrical has an advantage in obtaining a sufficient storage space for an electric charge. However, with an OCS (one cylinder storage) structure, for example, the height of the lower electrode must be increased to obtain a capacitance that is sufficient to enable operation of the device. For this purpose, a mold oxide thickness must be increased, and subsequently, a critical dimension (CD) of a bottom portion of a storage node hole in which the lower electrode is formed becomes smaller due to the sloping side wall that results when etching the storage node hole. Accordingly, the semiconductor device has an unstable shape with the lower electrode having a narrow lower portion. In addition, with such structure, the lower electrode is likely to collapse due to the occurrence of surface tension when removing the mold oxide by wet etching after forming the lower electrode in the storage node hole and drying is performed. Moreover, the weak lower electrode is likely to collapse or break due to thermal stress in subsequent processes. Consequently, the resulting semiconductor device may malfunction due to the occurrence of bridges between cells.